The present invention relates to a method of fabricating a semiconductor device and, more particularly, to a method of forming a high melting point metal or a refractory metal silicide film.
The integration density of semiconductor circuit device has been increasing more and more in the recent years by reducing or shrinking a size of each element. The reduction in size of an element, in particular a MOS transistor, is achieved by shortening the channel length thereof.
It has been known, however, that the reduction of channel length produces the so-called short channel effect which causes a substantial reduction of threshold value of a transistor. In order to prevent the short channel effect from occurring, it is required to reduce the diffusion depth. However, when the diffusion depth is reduced, the sheet resistance of a source/drain region is increased so that the operating speed of a circuit is substantially reduced.
In order to solve this problem, therefore, it has been disclosed in Japanese Patent Application Laid-open No. Sho 57-99775 to form a silicide layer on each of a gate, a source and a drain. This technique will be described briefly with reference to FIGS. 9a to 9f.
As shown in FIG. 9a, formed-on a P type silicon substrate 101 having resistivity of 50 .OMEGA.-cm are a field oxide film 102 and a gate oxide film 103. A phosphorus doped gate polysilicon 104 is formed on the gate oxide film 103. Source/drain regions 105 and 105' and a wiring region 105" are formed by ion-injection of As with density of 1.times.15 cm.sup.-2 at 40 KeV (FIG. 9b). Then, an SiO.sub.2 film 106 about 300 nm thick is formed on the whole surface of the wafer by CVD method (FIG. 9c). Thereafter, the SiO.sub.2 film 106 except portions thereof on side walls of the gate oxide film and the gate polysilicon is removed by an isotropic etching, so that the source/drain regions 105 and 105', the wiring region 105" and the gate polysilicon 104 are exposed (FIG. 9d).
Then, a tungsten (W) film 107 having a thickness of about 40 nm is vapor deposited on the whole surface of the wafer (FIG. 9e). Thereafter, this wafer is annealed in nitric atmosphere at, for example, 800.degree. C. for about one hour. During this annealing, a silicide forming reaction occurs in portions 108 of the tungsten film 107 which are in contact with the silicon and a tungsten silicide (WSi.sub.2) layer 109 having a thickness of about 110 nm is thus formed on substantially the whole surface of the source/drain regions 105 and 105' and the gate polysilicon 104 (FIG. 9f). Portions 110 of the tungsten film which are not reacted are they removed by treating it with acid. Thereafter, although not shown in the drawings, a PSG layer, contact holes and Al metallization, etc., are formed according to a usual fabrication method of an MOS transistor. Finally, a PSG film is provided as a protection film and bonding holes are formed, resulting in the MOS transistor. In this method, the sheet resistance of the source/drain portions is about 7 .OMEGA./.quadrature. which is very small compared with about 50 .OMEGA./.quadrature. of a diffusion layer, so that it is possible to reduce the depth of the source/drain diffusion layer. This technique by which a high melting point metal is deposited on a whole surface of a silicon wafer and a high melting point metal silicide is formed on only exposed surface of the silicon in self-alignment is referred to as SALICIDE (self-aligned silicide).
Other high melting point metal than tungsten, which may be used in this invention, includes molybdenum (Mo), titanium (Ti), etc.
An example of the annealing method for forming silicide by reacting a high melting point metal and silicon is disclosed in "Handotai Kenkyu 24", edited by Junichi Nishizawa/Handotai Kenkyu Shinkokai, published in 1986 by Kogyo Chosakai, p.207-239, which performs an annealing for a short time by using the lamp annealing. According to this method, it is possible to not only reduce the resistance of a film within a short time but also perform the annealing in an atmosphere whose purity is very high in view of prevention of oxidation. A relation between a sheet resistance of a titanium film 60 nm thick and an annealing temperature thereof when it is lamp-annealed in Ar atmosphere for 60 seconds is shown in FIG. 10. As will be clear from FIG. 10, the sheet resistance increases with increase of the annealing temperature up to around 575.degree. C. since silicon in the titanium is in solid solution due to an interface reaction between titanium and silicon and the crystal phase is not formed as yet, then is abruptly decreased at around 600.degree. C. in concomitant with a transition of silicon from solid solution phase through TiSi to TiSi.sub.2 (currently, this is considered as a phase transition from solid solution through crystal phase C-49 TiSi.sub.2 to crystal phase C-54 TiSi.sub.2) and becomes saturated when the final TiSi.sub.2 state is achieved.
According to a time dependency of the relation between sheet resistance value and annealing temperature shown in FIG. 11, the resistance value is decreased to saturation state within only 30 seconds when the thickness of the titanium film is in a range from 50 nm to 100 nm.
When this silicide technique is to be applied to a semiconductor device, it is important to prevent silicide formation on insulating films other than silicon from occurring. That is, it is possible to form silicide easily for a high melting point metal such as Pt, Pd, etc., belonging to VIIIa group, in which the metal is a diffusion seed and the formation is performed by reaction, while preventing silicide formation on an insulating film. However, when the silicide is formed by diffusion of silicon, a silicide reaction progresses toward a non-reacted metal side so long as silicon is supplied, basically, and a resultant silicide film may creep up on an edge of an oxide film as shown in FIG. 12 which shows a relation between a lamp-annealing time and a growth of silicide on the insulating film in lateral direction from the edge of the insulating film, resulting in degradation of self-alignment.
As a result, a silicide film formed on a source/drain regions creeps up along a side wall of a gate electrode and becomes in contact with a silicide film formed on the gate electrode, so that the short-circuit problem may occur between the source and the gate and between the drain and the gate. This phenomenon becomes considerable with increase of the fineness of pattern.
In order to avoid this problem, a two-step lamp-annealing method has been proposed. The two-step lamp-annealing method will be described with reference to FIGS. 13a to 13c. An oxide film is formed on a side wall of a polysilicon gate in the same manner as mentioned with reference to FIG. 9d. Then, a titanium film 107' having a thickness of 100 nm is formed in the same manner as mentioned previously (FIG. 13a). Thereafter, a resultant wafer is annealed at a relatively low temperature of about 600.degree. C. In this case, a portion of titanium, which becomes in contact with silicon, becomes silicide, resulting in a titanium silicide layer 109'. On the other hand, a titanium film 110' on an insulating film remains in a non-reacted state due to the low annealing temperature (FIG. 13b). Thereafter, the silicon and the non-reacted high melting point metal on the insulating film are selectively removed. Succeeding thereto, a second annealing is performed at a temperature of 650.degree. C. or more in order to reduce resistance of the silicide film and the silicide formation is completed (FIG. 13c).
FIG. 14 shows a change of sheet resistance of the silicide in the respective steps mentioned above. A titanium silicide of C-49 phase is formed by the first annealing, which is changed to a titanium silicide of C-54 phase by the second annealing, completing the silicide reaction.
The integration density of the integrated circuit has been increased and thus the size of element has been reduced correspondingly. With the reduction of element size, the film thickness and the aligning depth of diffusion layer are also made finer correspondingly. That is, with the reduction of element size, the thickness of titanium film is reduced. When the gate width becomes 300 nm or smaller and the titanium film becomes thinner, the annealing temperature in the second annealing is increased as shown in FIG. 15. With the increase of the second annealing temperature, crystal particles of TiSi.sub.2 are irreversibly re-arranged by heat and the so-called aggregation reaction of the particles occurs, so that it becomes difficult to reduce the resistance. When the aggregation reaction is considerable, there is a problem of breakage of wiring. This phenomenon becomes considerable with decrease of width of wiring and electrode and a decrease of titanium film thickness. A lower limit of the second annealing temperature is defined by a temperature at which the resistance of the silicide film is reduced by the transition from TiSi to Tisi.sub.2, that is, the phase transition from C-49 to C-54, and an upper limit is determined by the aggregation reaction. Particularly, when the pattern becomes as fine as having gate width of 0.3 .mu.m or less, the applicable range of this method becomes so narrow as shown in FIG. 15 that process conditions become very severe and a stable fabrication becomes difficult and, in an extreme case, the applicable range itself may disappear.
The SALICIDE process is a process by which resistance of a source electrode, a drain electrode, a gate electrode and a polysilicon wiring is reduced and can be formed in self-alignment. Nonetheless, it has been desired to develop another process which is adaptable to further reduction of element size with increase of integration density of an integrated semiconductor circuit device.